Note on Read Time-Stamp Counter

On Intel processors, there is an internally held counter, namely the Time Stamp Counter (TSC), which can be read out with a simple Read Time-Stamp Counter (RDTSC) assembler instruction. It holds a 64-bit counter of cycles since the processor was booted. I've seen legacy code that uses this instruction directly to implement performance measurements, so don't be surprised if you encounter this instruction out in the wild—it is just super-fast! However, there are some problems when we try to read that counter directly on modern pipelined and multicore CPUs, as there's simply no guarantee that a thread will start and end its execution on the same core!